BACKGROUND OF THE INVENTION

The present invention relates to a static semiconductor memory device in which erroneous writing in cells is prevented.

In a bipolar type static RAM (random access memory), memory cells are arranged at the intersections of word lines and pairs of bit lines. Each memory cell is formed by a flip-flop circuit including a pair of multiemitter transistors, load resistors, and Schottky barrier diodes connected to the load resistors in parallel.

Recent increases in the capacity of static RAM's have led to increases in the resistance value of the load resistors. In a conventional static RAM, however, a problem arises when, for example, a memory cell M.sub.11 is selected by selecting a word line W.sub.1 and a column B.sub.1 soon after a memory cell M.sub.00 is selected by selecting a word line W.sub.0 and a column B.sub.0. In such a case, a memory cell M.sub.01, connected to the word line W.sub.0 and column B.sub.1, is temporarily selected before the intended memory cell M.sub.11 is selected. This is because column selection is generally faster than word line selection. In such a conventional static RAM, there is a possibility of erroneous writing in the selected cell M.sub.11 as is explained below.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a static semiconductor memory device in which erroneous writing in cells is prevented.

For the purpose of achieving the object of the present invention, a static semiconductor memory device, which includes static memory cells respectively connected to a pair of word lines and a pair of bit lines, further comprises a pair of unidirectional current elements, each having one end connected to one of the pair of bit lines, so as to absorb the electric current from the bit line. The other end of each unidirectional current element is commonly connected to a constant current source via a switching means which is switched by a column-selecting voltage.

Further features and advantages of the present invention will be apparent from the ensuing description with reference to the accompanying drawings to which, however, the scope of the invention is in no way limited.

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 is a block diagram of a conventional static RAM;

FIG. 2 is a circuit of memory cells included in the RAM shown in FIG. 1;

FIGS. 3A, 3B and 3C are waveform timing charts showing changes of potentials at the respective parts of the memory device shown in FIGS. 1 and 2;

FIG. 4 is a block diagram of one embodiment of a static semiconductor memory according to the present invention; and

FIG. 5 is a block diagram of another embodiment of the static semiconductor memory according to the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

A conventional bipolar type static RAM comprises a plurality of memory cells M.sub.00, M.sub.01, . . . arranged at the intersections of word lines W.sub.0, W.sub.1, . . . and pairs of bit lines B.sub.00 and B.sub.01, B.sub.10, and B.sub.11, . . . , as shown in FIG. 1. In FIG. 1, W.sub.0h, W.sub.1h, . . . represent negative side word lines or hold lines; WD.sub.0, WD.sub.1, . . . represent word drivers; Q.sub.3 and Q.sub.4 and Q.sub.5 and Q.sub.6 represent column-selecting transistors; Y.sub.0, Y.sub.1, . . . represent column-selecting voltages; and I1 and I2 represent constant current sources. The pairs of bit lines B.sub.00 and B.sub.01, B.sub.10 and B.sub.11, . . . , are connected to the emitters of bit drivers Q.sub.10, Q.sub.11, Q.sub.12, and Q.sub.13. The bases of the bit drivers Q.sub.10, Q.sub.11, Q.sub.12, and Q.sub.13 are connected to a write amplifier 1, and the collectors of the bit drivers Q.sub.10, Q.sub.11, Q.sub.12, and Q.sub.13 are connected via transistors Q.sub.15 and Q.sub.16 to a sense amplifier 2. The bases of the transistors Q.sub.15 and Q.sub.16 receive a reference voltage V.sub.R, and the collectors of the transistors Q.sub.15 and Q.sub.16 are connected via load resistors R.sub.11 and R.sub.12 to electric sources.

FIG. 2 is a detailed circuit diagram of the memory cells M.sub.01 and M.sub.11 shown in FIG. 1. As shown in FIG. 2, memory cells M.sub.01, M.sub.02 are formed by flip-flop circuits, each including load resistors R.sub.1a, R.sub.2a ; R.sub.1b, R.sub.2b, Schottky barrier diodes D.sub.1a, D.sub.2a ; D.sub.1b, D.sub.2b, and multiemitter transistors Q.sub.1a, Q.sub.2a ; Q.sub.1b, Q.sub.2b.

In the static RAM shown in FIGS. 1 and 2, a problem arises when, for example, the memory cell M.sub.11 is selected by selecting the word line W.sub.1 and the column B.sub.1 soon after the memory cell M.sub.00 is selected by selecting the word line W.sub.0 and the column B.sub.0. In such a case, the memory cell M.sub.01, connected to the word line W.sub.0 and the column B.sub.1, is temporarily selected before the intended memory cell M.sub.11 is selected. This is because column selection is generally faster than word line selection. In such a conventional static RAM, there is a possibility of erroneous writing in the selected cell M.sub.11 as is explained below.

That is, suppose the write data is supplied so that, in each of the memory cells M.sub.01 and M.sub.11, the transistors Q.sub.1a, Q.sub.1b, on the left side in FIG. 2, are turned on and the transistors Q.sub.2a, Q.sub.2b, on the right side in FIG. 2, are turned off. A high (H) voltage level then is maintained at the points b.sub.1, b.sub.2 in the cells, and a low (L) voltage level then is maintained at the points a.sub.1, a.sub.2 in the cell. Since the transistors Q.sub.1a, Q.sub.1b are in the "on" state, their collector currents flow through the high resistors R.sub.1a, R.sub.1b. Significant voltage drops across the resistors R.sub.1a and R.sub.1b turn on the Schottky barrier diodes D.sub.1a, D.sub.1b. On the other hand, since the transistors Q.sub.2a, Q.sub.2b are in the "off" state, their collector currents do not flow through the high resistors R.sub.2a, R.sub.2b and, therefore, the Schottky barrier diodes D.sub.2a, D.sub.2b are in the off state. Accordingly, the impedance of the points a.sub.1, a.sub.2 is low while the impedance of the points b.sub.1, b.sub.2 is high. Therefore, when the row W.sub.1 is selected, the potential at the point a.sub.2 in the memory cell M.sub.11 rises faster than that at the point b.sub.2 in the memory cell M.sub.11 as shown in FIG. 3B. Before the column is selected, both the bit lines B.sub.10 and B.sub.11 are clamped at a high voltage by clamp circuits Q.sub.21 and Q.sub.22, but selection of the column releases this clamping. Since the selecting speed on the column is faster than that on the word line, as shown in FIGS. 3A and 3B, the potential of the bit line B.sub.10 is clamped by the memory cell M.sub.01 and is maintained at a high level, while the potential of the bit line B.sub.11 is maintained at a low level, as shown in FIG. 3C, as determined by the base potential of the transistor Q.sub.13 (FIG. 1), so that not the word line W.sub.0 but the word line W.sub.1 is selected. However, the potential of the bit line B.sub.10 is still kept high because of a capacitance attached to the bit line, and the potential of the bit line B.sub.11 is maintained at a low level as determined by the transistor Q.sub.13. In this circumstance, the potential difference between the point a.sub.2 and the bit line B.sub.10 is kept in the low bias voltage state, and the potential difference between the point b.sub.2 and the bit line B.sub.11 is kept in the high bias voltage state. Therefore in the case where the above difference resides between the bit lines B.sub.10 and B.sub.11, during the selection of the memory cell M.sub.11 from the side of the word line W.sub.1, the bit line B.sub.10 is at a high level and the bit line B.sub.11 is at a low level. Therefore, there is a possibility that the transistor Q.sub.1b may be turned off and the transistor Q.sub.2b may be turned on in the selected cell M.sub.11.

The present invention is meant to solve this problem. FIG. 4 is the block diagram of one embodiment of the present invention. In FIG. 4, M.sub.i0 and M.sub.i1 represent a memory cell placed at i row and 0 column and a memory cell placed at i row and 1 column, respectively. Each memory cell has the same structure as that of the above-mentioned memory cells M.sub.01, M.sub.11, etc. W.sub.i designates a word line of row i, and WD.sub.i represents a driver for the word line W.sub.i. In the present invention, diodes D.sub.3 and D.sub.4, D.sub.5 and D.sub.6, . . . are connected to the paired bit lines B.sub.00 and B.sub.01, B.sub.10 and B.sub.11, . . . with the polarity shown in the drawings, and common connection ends of these diodes are connected to a constant current source I.sub.3 through transistors Q.sub.7, Q.sub.8, . . . . These diodes D.sub.3 and D.sub.4 or D.sub.5 and D.sub.6, . . . form a current switch together with the constant current source I.sub.3. Furthermore, the transistors Q.sub.7, Q.sub.8, . . . , are controlled by column-selecting signals Y.sub.0, Y.sub.1, . . . in the same way as the transistors Q.sub.3 and Q.sub.4, Q.sub.5 and Q.sub.6, . . . .

When the diodes D.sub.3 and D.sub.4, D.sub.5 and D.sub.6, . . . are connected to the corresponding pairs of the bit lines so that current switches are formed as described above, if the level of one bit line becomes higher than the level of the other bit line at the time of selection of the column, the diode connected to the one bit line is turned on to inhibit elevation of the potential. Accordingly, in this embodiment, the level of the bit line B.sub.10 is abruptly lowered, as indicated by the dotted line B'.sub.10 in FIG. 3C, thereby preventing the case where the transistor Q.sub.1b is turned off and the transistor Q.sub.2b is turned on in the selected cell M.sub.11.

The diodes D.sub.3 and D.sub.4, D.sub.5 and D.sub.6, . . . absorb the current from the bit lines, in other words, discharge the stored charges in the bit lines, but this discharge is effected only when the corresponding column is selected by the transistors Q.sub.7 and Q.sub.8. The diodes are not actuated when the corresponding column is not selected. Accordingly, there is no problem of increase in the power consumption. Moreover, writing or reading is not disturbed at all. For example, in the case of reading, if the memory cell M.sub.i0 is selected by maintaining the word line W.sub.i and column-selecting voltage Y.sub.0 at high levels and by turning on the transistors Q.sub.3 and Q.sub.4, and in the memory cell M.sub.i0, the left transistor (for example Q.sub.1b in FIG. 2) is in the "on" state while the right transistor (for example Q.sub.2b in FIG. 2) is in the "off" state, a current I.sub.1 flows through WD.sub.i, W.sub.i, M.sub.i0, B.sub.00 and Q.sub.3 ; and a current I.sub.2 flows through the reading transistor Q.sub.11, bit line B.sub.01 and transistor Q.sub.4, but no current flows in the reading transistor Q.sub.10 (ordinarily, I.sub.1 is equal to I.sub.2). A sense amplifier 2 shown in FIG. 4 detects the electric current flows in the transistors Q.sub.10 and Q.sub.11, and a reading output is produced. In addition to the above-mentioned currents I.sub.1 and I.sub.2, a currents I.sub.3 flows through WD.sub.i, M.sub.i0, B.sub.00, D.sub.3, and Q.sub.7 in the present invention. However, the current-flowing state of the transistor Q.sub.10 or Q.sub.11 is not influenced by this current I.sub.3. Reading is accomplished by selecting the memory cell, for example, M.sub.i0, in the same manner as described above, that is, by lowering the potential of the bit line B.sub.01 to turn on the right transistor of the cell and elevating the potential of the bit line B.sub.00 to turn off the left transistor of the cell (changes in the potentials of these bit lines occur according to the base potentials of the transistors Q.sub.10 and Q.sub.11). In the present embodiment, the current I.sub.3 flows through the transistor Q.sub.10 only when the level of one of the paired bit lines is lowered and, simultaneously, the level of the other bit line is elevated. Actuation and de-energization of the transistors and of the cell are not adversely affected by this current I.sub.3.

FIG. 5 illustrates another embodiment of the present invention, in which resistors R.sub.3, R.sub.4 are connected to the diodes, and a current I.sub.4 is divided into currents I.sub.5 and I.sub.6, whereby the same effect as that attained in the embodiment shown in FIG. 4 is attained. Incidentally, the values of the resistors R.sub.3 and R.sub.4 are determined so that relations of I.sub.5 =I.sub.1 +I.sub.3 and I.sub.6 =I.sub.2 are established.

As will be apparent from the foregoing description, according to the present invention, occurrence of erroneous writing in a memory cell, which is likely to occur when reading is carried out by selecting the memory cell by changing word lines and column lines, can be prevented simply and assuredly. Therefore, the present invention is very advantagesous.