BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of the transient detector apparatus according to the present invention;

FIG. 2 is a graphical representation of the timing relationship of key signals in the circuit shown in FIG. 1;

FIG. 3 is a block diagram showing the transient detector apparatus in greater detail;

FIGS. 4a-4c are a schematic diagram of the composite amplifier;

FIG. 4 is an illustration of the manner in which FIGS. 4a-4c are arranged to provide a complete schematic diagram;

FIGS. 5a-5d are a schematic diagram of the peak detector unit and a portion of the slope detector unit;

FIG. 5 is an illustration of the manner in which FIGS. 5a-5d are arranged to provide a complete schematic diagram;

FIGS. 6a-6c are schematic diagrams of the encoder unit, a portion of the slope detector and the logic control unit;

FIG. 6 is an illustration of the manner in which FIGS. 6a-6c are arranged to provide a complete schematic diagram;

FIG. 7 is a schematic diagram of the counter control unit, the peak detector reset unit, the system reset unit, and the timing register unit;

FIG. 8 is a schematic diagram of the overflow indicator unit;

FIG. 9 is a schematic diagram of the positive/negative data select unit;

FIGS. 10a-10c are schematic diagram of the inverter select unit, the OR gates, the pulse width measurement/register units, the first data register unit, the AND gates, the timing register units, the comparator unit, the second data register unit and the timing control regulator unit;

FIG. 10 is an illustration of the manner in which FIGS. 10a-10c are arranged to provide a complete schematic diagram;

FIGS. 11a-11c are a schematic diagram of the third data register unit, the comparator unit 52, and the output data register unit;

FIG. 11 is an illustration of the manner in which FIGS. 11a-11c are arranged to provide a complete schematic diagram;

FIGS. 12a-12d are a schematic diagram of the third data register unit 50, a portion of which is also shown in FIG. 11c; and,

FIG. 12 is an illustration of the manner in which FIGS. 12a-12d are arranged to provide a complete schematic diagram.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring now to FIG. 1, there is shown a block diagram of the transient detector apparatus wherein the input signal is applied to the input monitor probe 110. The logic input signal which may comprise a dynamic logic signal is applied to the signal conditioner unit 112. In the signal conditioner unit 112, the logic input signal is examined to determine the correct logic level of the digital bits in the logic input signal. Thus, the signal conditioner unit 112 generates corrected logic one and logic zero levels for signal levels which meet the respective conditions and criteria for a logic one or zero. On the basis of that determination, the remaining (levels that did not qualify as logic signals) signal levels are considered unwanted transient signals that are present in the logic input signal. The output signal from the signal conditioner unit 112 is simultaneously applied to the slope detector unit 114 and the switch unit 116. The slope detector unit 114 is activated by the input signal and generates a digital pulse signal which is proportional to the slope of the input signal. The digital pulse signal from the slope detector unit 114 is applied to both the counter unit 120 and the logic unit 121. The logic unit 121 determines whether the digital pulse signal represents a logic signal or a transient signal. When the logic unit 121 determines that the digital pulse signal is a transient signal, it generates a validate signal which is sent to the control unit 130. When the digital pulse signal from the slope detector unit 114 represents a logic signal, the logic unit 121 outputs a restore signal to the control unit 130.

The counter unit 120 applies the digital pulse signal to the width unit 122 when the logic unit 121 provides a transient detected signal to the counter unit 120. The width unit 122 measures and determines the pulse width of the transient signal which is represented by the digital pulse signal from the counter unit 120. The width unit 122 outputs a digital signal which represents the pulse width of the transient signal upon receipt of a control signal from the logic unit 121.

The switch unit 116 which receives the input signal from the signal conditioner unit 112, applies the input signal to one of the peak detector units 124 or 126. The peak detector units 124, 126 provide an enable signal to the control unit 130 to indicate which peak detector unit has received the input signal therein. When the control unit 130 receives a validate signal from the logic unit 121, it signals the peak detector unit to send the peak signal level therein to the A/D converter unit 128. The A/D converter unit converts the peak signal level to a digital amplitude signal. The output from the A/D converter unit 128 is applied to the amplitude unit 132. The amplitude unit 132 provides an amplitude output signal which represents the amplitude of the detected transient signal that was present in the input signal. A timing unit 118 which receives an external synch signal provides timing signals to the logic unit 121, the switch unit 116, and the A/D converter unit 128.

The transient detector apparatus operates in the following manner. The signal of interest is monitored with a high impedance, wide bandwidth probe 110. The output from the input monitor probe 110 is fed to the signal conditioner unit 112. The signal conditioner unit 112 drives a slope detector unit 114 and either peak detector unit 124 or 126 by means of switch unit 116. The peak detector units 124, 126 contain a charge transfer device which outputs a signal whenever the input signal is larger than any previously stored signal. The peak detector unit has a control capability that allows any peak value to be discarded or saved at the discretion of the control circuit 130. The slope detector unit provides a slope signal to the logic unit. The logic unit utilizes the slope signal to determine whether a signal is a valid logic transition or a transient signal. It monitors the signal under test in terms of signal amplitude and slope. If the input voltage crosses ninety percent of the full scale value before a slope reversal occurs, the logic unit outputs a restore signal indicating that a normal logic transition occurred. This restore signal will signal the control unit 130 to discard the logic level which is stored in the peak detector. The restore signal permits the control unit 130 to reset the charge transfer device (located within the peak detector) and thereby prepare it for the next input signal transition. If the logic unit 121 encounters a slope reversal prior to reaching the ninety percent point of the full scale signal value, it will output a validate signal to the control unit 130 which will signal the peak detector to store this peak value as a transient. Once a transient value is stored and validated, only transient signals of a larger value (within a given period of time) can cause a peak detector output.

The charge transfer device, which is located within the peak detector unit, has a time limited storage accuracy. Therefore, it is necessary to alternate between two of these devices. This is accomplished by means of an analog switch 116. Every millisecond the stored value of one of the devices is digitalized and stored while the second device is used to monitor the signal under test. This procedure is alternated every millisecond and the largest peak amplitude and the associated pulse width is maintained in digital storage (width unit 122 and amplitude unit 126) until interrogated by the user. When this occurs the storage registers 122, 126 will output two eight bit words which are a measurement of transient amplitude and pulse width. The transient peak amplitude is accurate to five percent and the pulse width is accurate to 4 nanoseconds.

There is shown in FIG. 2 is a timing diagram which depicts the key circuit functions. The first signal (SIG IN) is a typical logic signal that would be monitored by the transient detector. The second signal (PEAK DETECTOR OUTPUT) is a result of what occurs as a function of the SIG IN. The peak detector output is proportional to the difference in the last transient stored and the peak of the new input signal. The third signal (CONTROL) occurs whenever a transient has been validated. The fourth signal (RESTORE) occurs whenever a logic signal returns to a predetermined level.

Turning now to FIG. 3, there is shown a detailed block diagram of the transient detector apparatus. The logic input signal which is fed to the composite amplifier unit 10 is utilized to drive both the peak detector unit 12 and the slope detector unit 14. the peak detector unit 12 captures and holds the analog transient amplitude value which may be present in the logic input signal and converts the analog value to a digital equivalent. The output from the peak detector unit 12 is converted to a five (5) bit digital word by the encoder unit 16 and then is sent to the inverter select unit 24. If the transient data was from a negative transient, the logic level signal from the logic control unit 48 will invert the transient data through the inverter select unit 24. The amplitude data is then stored in the first data register unit 30 and then compared to the transient data in the second data register unit 44 to determine if the transient data in the second data register unit 44 should be updated. After every logic transition, the amplitude data in the second data register 44 is transferred to the third data register unit 50 for temporary storage. The output of the third data register unit 50 is then compared with the data in the output data register unit 54 to determine whether the output data register unit 54 should be updated.

The slope detector unit 14 drives the logic control unit 48 in which several logic decisions are made. The logic control unit 48 decides:

a. If the transient originated from the upper logic level or the lower logic level.

b. If the data should be inverted or not.

c. Tells the counter control unit 18 when to start and stop the pulse width measurement which occurs in pulse width measurement unit 28a.

d. Zero sets the first data register unit 30 after a logic transition.

e. Tells the peak detector reset unit 20 to clear the peak detector unit 12 after a logic transition.

f. Transfer transient data to the first data register unit 30 when a slope change is detected.

The pulse width measurement unit 28a is used to capture the pulse width and signal the over flow indicator unit 32 if the pulse width exceeds a given width. The pulse width is then transferred to the pulse width register unit 28b if the pos/neg data select unit 38 decides that it should be transferred. The pulse width register unit 28b is updated everytime the third data register unit 50 is updated. The peak detector unit 12 can be reset either from an external signal through the system reset unit 22 or internally from the peak detector reset unit 20 when a logic change signal occurs.

Schematic diagrams for the units which are shown in FIG. 3 are presented according to the following table:

                  TABLE I
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    Unit                   FIG.
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    composite amplifier unit 10
                           4a, 4b, 4c
    peak detector unit 12  5a, 5b, 5c, 5d
    slope detector unit 14 5d, 6c
    encoder unit 16        6a, 6b, 6c
    counter control unit 18
                           6c, 7
    peak detector reset unit 20
                           7
    system reset unit 22   7
    inverter select unit 24
                           10a
    OR gate unit 26        10a
    pulse width measurement unit 28a
                           10b
    pulse width register unit 28b
                           10b
    first data register unit 30
                           10c
    overflow indicator unit 32
                           8
    timing register unit 34
                           10a
    AND gate unit 36       10c
    pos/neg data select unit 38
                           9
    timing register unit 40
                           7
    comparator unit 42     10c
    second data register unit 44
                           10c
    timing control regulator unit 46
                           10c
    logic control unit 48  6c
    third data register unit 50
                           11a, 12d, 12b
    comparator unit 52     11c
    output data register unit 54
                           11c
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