TECHNICAL FIELD OF THE INVENTION

The present invention relates in general to electronic circuits and in particular to voltage generation circuits and methods.

BACKGROUND OF THE INVENTION

Integrated circuit systems which include analog devices and which employ only a single voltage power supply require the generation on-chip of a mid-supply voltage for use as an analog ground (AGND) reference. One simple method to provide the mid-supply voltage is through a voltage divider consisting of two equally valued resistors connected in series between the positive voltage supply (i.e., the positive rail) and ground. One way of fabricating these resistors is to use the nsemiconductor in which p-MOS devices are normally fabricated. While the n- resistors have the advantage of being small, they suffer from the substantial disadvantage of having a high voltage coefficient. This voltage coefficient has two primary components, first, the end-to-end voltage coefficient due to the voltage drop across the resistor when current flows, and second, a backgate or body effect component due to reverse biasing from the channel of the resistor and the substrate. The component of the voltage coefficient caused by the backgate or body effect is the more serious problem, since it causes the two resistors to have different resistance values, even though the resistors have equal physical size, due to the pinching effect of the depletion region between the channel and the substrate.

A second option is to use polysilicon resistors. The use of polysilicon resistors eliminates the problem of the backgate or body effect component of the overall voltage coefficient; however, the end-to-end component of the voltage coefficient remains. Polysilicon resistors also have the significant disadvantage of being larger in physical size. Further, the output impedance of the analog reference must be minimized to insure a stable voltage even when the loads are switching at high frequencies. For improved operation at high frequencies, a pair of capacitors in parallel with each of the resistors can be added to lower the AC impedance at the tapping point of the voltage divider. Even with the addition of the capacitors, however, the a.c. impedances may still be relatively high for ground impedances. Finally, the addition of capacitors makes the voltage generation circuitry significantly larger, especially if current on the order of a milliamp or more is required. Depending on current requirements, the size of the capacitors, and the layout of the remainder of the integrated circuitry, there may be only enough space on-chip for a single, large mid-rail voltage generation circuit. Unless the output impedance of the voltage generator is substantially lower, a single voltage generator will result in cross-talk between the various circuits being supplied.

Thus, the need has arisen for circuitry and methods for generating voltages for use as analog ground references. Such circuitry and methods would provide for the generation of mid-rail voltage using a minimal amount of space while at the same time presenting a low output impedance even at high frequency.

SUMMARY OF THE INVENTION

According to the invention, a voltage generation circuit is provided which includes a first plurality of transistors having source/drain paths coupled in series to establish a first current path between a first voltage and a second voltage rail. The first transistors are provide a pre-selected intermediate voltage at a node along the first current path. A second plurality of transistors are provided having source/drain paths coupled in series to establish a second current path between the rails and coupled to the first transistors such that current flow in the second current path mirrors current flow in the first current path. The second plurality of transistors a provide voltage substantially equal to the intermediate voltage at a node along the second current path. A pair of output transistors are provided having source/drain paths coupled in series to establish a third current path between the voltage rails. A first one of the output transistors is coupled as a current mirror with a first one of the second plurality of transistors. A second one of the output transistors is coupled as a current mirror with a second one of the second plurality of transistors. First and second output transistors provide a voltage substantially equal to the intermediate voltage at an output node coupling the source/drain paths of the output transistors. The preferred embodiments of the present invention provide significant advantages over prior art voltage generation circuits.

The preferred embodiments of the present invention provide for the generation of a midrail voltage using a minimum amount of space on the integrated circuit, while at the same time presenting a low output impedance, even at high frequency.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIG. 1 is an electrical schematic drawing of an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The preferred embodiment of the present invention and its advantages are best understood by referring to FIG. 1 of the drawings, like numerals being used for like and corresponding parts of the various drawings.

Referring to FIG. 1, a mid-rail voltage generator according to the invention is shown generally at 10. Voltage generator 10 includes diode connected (i.e., having the gate shorted to drain) p-channel transistors 10 12, 14, 16 and 18, establishing a current path between a high voltage rail V.sub.DD and a low voltage rail V.sub.SS. In the illustrated embodiment, the high voltage rail is at +5 volts, and the low voltage rail at ground. In alternate embodiments, the high and low voltage rails may differ, such as being set at +10 volts and 0 volts respectively.

As a general approximation: ##EQU1## where: I.sub.DS = current through the source-drain path;

V.sub.GS = the gate to source voltage;

V.sub.T = the threshold voltage for the device;

.mu.= effective electron mobility of the channel for an n-channel device or in the alternative, the effective hole mobility of the channel for a p-channel device;

C.sub.O = gate capacitance per unit area;

W = length of the channel; and

L = length of the channel.

For a given fabrication process .mu.C.sub.O and V.sub.T are essentially constant such that the current I.sub.DS through a given field effect transistor for a given gate to source voltage V.sub.GS (or in the alternative the gate to source voltage V.sub.GS for a given current I.sub.DS) becomes primarily function of the width and length of the transistor channel.

In the illustrated embodiment of voltage generator 10, transistors 12-18 are matched, each having a transistor channel width to length ratio of 20:1, resulting in the voltage at node A being substantially half of the supply voltage V.sub.DD. The current flow through transistor 12 is then mirrored into transistor 20 establishing current flow between the voltage rails through transistors 20, 22, 24 and 26.

In the illustrated embodiment, transistors 20, 24 and 26 are matched to transistors 12-18 such that the current flow between the two parallel current paths is approximately equal. This configuration uses the least power; however, in alternate embodiments, transistor 20 can be scaled in size relative to transistor 12 to produce a current gain. Transistors 24 and 26 are then scaled in size relative to transistors 16 and 18 respectively, such that the voltage a node B substantially equals the voltage at node A (the mid-supply voltage).

Transistors 28 and 30 are the output devices for circuit 10. Transistor 28 mirrors the current flow in transistor 22, while transistor 30 mirrors the current flow in transistor 24. By matching the relative scaling in size between transistors 22 and 28 with the relative scaling in size between transistors 24 and 30, the output voltage V.sub.AGND is forced to the mid-supply (mid-rail) voltage. In the illustrated embodiment, transistors 28 and 30 have channel width to length ratios of eight times (i.e. n=8) the channel width to length ratios of transistors 22 and 24 resulting in a current gain of approximately eight. In alternative embodiments, the scaling in size between transistors 22 and 24 and transistors 28 and 30, respectively can be modified to vary the current gain. Advantageously, the output of circuitry 10 is provided by the common sources of transistors 28 and 30 which gives circuitry 10 a low output impedance (the output impedance R.sub.O approximating the inverse of the output transconductance or 1/g.sub.m).

For improved matching between the relative scaling in size between transistors 22 and 28 and the relative scaling in size between transistors 24 and 30, transistors 28 and 30 preferably comprise a series of parallel transistors, each parallel transistor substantially equivalent in size (i.e., having equivalent channel widths and lengths) to transistors 22 and 24 respectively. For example, in the illustrated embodiment where n=8, transistor 28 comprises eight parallel transistors each equivalent to transistor 22, and transistor 30 comprises eight parallel transistors each equivalent to transistor 24.

The only variation in setting the output voltage V.sub.AGND to half of the supply voltage V.sub.DD comes from the differences in conduction between transistors 28 and 30 (which includes differences in transconductance and output conductance due to channel length modulation). The transconductance between n-channel transistor 28 and p-channel transistor 30, which carry the same current, can be matched by equaling the betas (where .beta. = .mu.C.sub.O W/L). To reduce problems with differing output conductance due to channel length modulation, longer channel lengths can be selected if speed and size are not critical.

Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.