FIELD OF THE INVENTION

The present invention relates to a method and /or architecture for macro-cell flip-flops generally and, more particularly, to a method and/or architecture for a macro-cell flip-flop with a scan-in input.

BACKGROUND OF THE INVENTION

A programmable logic device (PLD) provides an economical and efficient means for implementing predetermined Boolean logic functions in an integrated circuit. Such a device consists of, generally, an AND plane configured to generate predetermined product terms in response to a plurality of inputs, a group of fixed/programmable OR gates configured to generate a plurality of sum-of-products(SOP) terms in response to the product terms, and a number of logic elements (i.e., macro-cells) configured to generate a desired output in response to the sum-of-products terms. The output of the macro-cells may be presented at an I/O pin or routed back to the AND plane. The sum-of-products terms can also be generated using programmable NOR-NOR or NAND-NAND logic.

Each macro-cell can contain a flip-flop called a macro-cell flip-flop. Testing the functionality of the macro-cell and surrounding logic is required. Scan test procedures are conducted to test the macro-cells and surrounding logic without increasing the device pin count. One such scan test procedure is an IEEE std 1149.1 JTAG (referred to herein as JTAG) boundary scan test. A JTAG boundary scan test is conducted with JTAG test instrumentation connected to I/O pins of the PLD.

Referring to FIG. 1, a block diagram of a conventional PLD 10 is shown. The PLD 10 has a number of macro-cells 12a-12n. Each of the macro-cells 12a-12n may be associated with an I/O pin 14a-14n. Each macro-cell has three boundary scan registers 16a-16n and an associated macro-cell flip-flop 18a-18n. Test data is shifted in and out of the flip-flops 18a-18n of each macro-cell 12a-12n using the scan registers 16a-16n. The conventional method of testing a PLD requires either a direct connection of the macro-cells 12a-12n to I/O pins 14a-14n and/or additional boundary scan registers 16a-16n. Since three boundary scan registers 16a-16n are used for each macro-cell flip-flop 18a-18n, three clock cycles are required for each test data bit to be shifted through each macro-cell 12a-12n.

Modern PLDs continue to increase in complexity. The increasing complexity causes increased difficulty in providing direct access to the content of each macro-cell from a dedicated I/O pin. For example, a modern PLD can have, in one example, over 1500 macro-cells but less than 500 I/O pins. A solution that provides a scan chain made up of all the macro-cells of a PLD with a minimum number of I/O pins would be desirable. A solution that can use the available flip-flop resource of a macro-cell, without requiring additional boundary scan registers would also be desirable.

SUMMARY OF THE INVENTION

The present invention concerns a programmable logic device comprising a macro-cell flip-flop configured to store (i) a first input when the programmable logic device is in a normal mode and (ii) a second input when the programmable logic device is in a test mode.

The objects, features and advantages of the present invention include providing a method and/or architecture for a macro-cell flip-flop with a scan-in input that may (i) provide an easily accessible internal scan test interface, (ii) improve testability of the macro-cells and surrounding logic inside a PLD, (iii) eliminate the requirement for a one-to-one correspondence between I/O pins and macro-cells, (iv) be configured as a part of regular logic or a test scan chain, (v) easily form a test scan chain, containing all the macro-cells of a PLD, (vi) not require additional registers for a scan operation, and/or (vii) be asynchronously reset or preset.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects, features and advantages of the present invention will be apparent from the following detailed description and the appended claims and drawings in which:

FIG. 1 is a block diagram illustrating a macro-cell scan chain implementation in a conventional programmable logic device;

FIG. 2 is a block diagram illustrating a preferred embodiment of the present invention;

FIG. 3 is a detailed block diagram illustrating the preferred embodiment of a macro-cell flip-flop of FIG. 2;

FIG. 4 is a schematic diagram of a preferred embodiment of a macro-cell flip-flop of FIG. 3; and

FIG. 5 is a block diagram illustrating a scan chain implemented in accordance with the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIG. 2, a block diagram of a circuit 100 is shown in accordance with a preferred embodiment of the present invention. The circuit 100 may be implemented, in one example, as a macro-cell flip-flop of a programmable logic device (PLD). The circuit 100 may have, in one example, an input 102 that may receive a signal (e.g., XORIN), an input 104 that may receive a signal (e.g., SCANIN), an input 106 that may receive a signal (e.g., CLK), an input 108 that may receive a signal (e.g., GINTSCNEN), an input 110 that may receive a signal (e.g., PRESETB), an input 112 that may receive a signal (e.g., RESETB), an input 114 that may receive a signal (e.g., GRESETB), an output 116 that may present a signal (e.g., DOUT), and an output 118 that may present a signal (e.g., DOUTB). The signal XORIN may be, in one example, a data signal. The signal SCANIN may be, in one example, a scan test data signal. The signal CLK may be, in one example, a clock signal. The signals GINTSCNEN, RESETB, PRESETB, and GRESETB may be, in one example, control signals. The circuit 100 may be configured, in one example, to (i) select the signal XORIN or the signal SCANIN, (ii) register (e.g., store) the signal selected (e.g., XORIN or SCANIN), and (iii) propagate the signal selected as the signal DOUT in response to one or more of the signals CLK, GINTSCNEN, RESETB, GRESETB, and PRESETB. The circuit 100 may be configured, in one example, to select (i) the signal XORIN when the PLD is operating in a normal mode or (ii) the signal SCANIN when the PLD is operating in a test mode. The circuit 100 may be configured to asynchronously (i) deselect the signals XORIN and SCANIN and (ii) place the signal DOUT in a first logic state (e.g., HIGH, or a digital "1") or a second logic state (e.g., LOW, or a digital "0") in response to one or more of the signals RESETB, GRESETB, and PRESETB. The signal DOUTB may be the digital complement of the signal DOUT.

Referring to FIG. 3, a detailed block diagram of the circuit 100 is shown. In one example, the circuit 100 may comprise a circuit 120, a circuit 122, and a circuit 124. The circuit 120 may be implemented, in one example, as a reset circuit. The circuit 122 may be implemented, in one example, as a multiplexer circuit. The circuit 124 may be implemented, in one example, as a D-type flip-flop circuit. However, other types of flip-flops may be implemented to meet the design criteria of a particular application. For example, the circuit 124 may be implemented as a configurable D/T/T-bar flip-flop or a latch. The circuit 120 may have an input 126 that may receive the signal RESETB, an input 128 that may receive the signal GRESETB, an output 130 that may present a signal (e.g., MRESET) to an input 132 of the circuit 122, and an output 134 that may present a signal MRESETB to an input 136 of the circuit 124. The circuit 120 may be configured to generate the signals MRESET and MRESETB in response to the signals RESETB and GRESETB. The signals MRESET and MRESETB may be digital complements.

The signals GINTSCNEN, XORIN, and SCANIN may be presented to the circuit 122: The circuit 122 may have an input 138 that may receive the signal RESETB, an input 140 that may receive the signal GRESETB, an input 142 that may receive the signal PRESETB, and an output 146 that may present a signal (e.g., DIN) to an input 148 of the circuit 124. The signal DIN may be used as an intermediate signal. The circuit 122 may be configured, in one example, to select the signal XORIN or the signal SCANIN as the signal DIN in response to one or more of the signals GINTSCNEN, PRESETB, RESETB, GRESETB, and MRESETB. The circuit 122 may be configured to asynchronously (i) deselect the signals XORIN and SCANIN and (ii) place the signal DIN in a first logic state (e.g., HIGH, or a digital "1") or a second logic state (e.g., LOW, or a digital "0") in response to one or more of the signals PRESETB, RESETB, GRESETB, and MRESETB.

The circuit 124 may have an input 144 that may receive the signal PRESETB and a clock input that may receive the signal CLK. The circuit 124 may be configured to present the signals DOUT and DOUTB in response to one or more of the signals PRESETB, DIN, CLK, and MRESETB.

The signals GRESETB, RESETB, and PRESETB may be used to asynchronously place the signals DIN, DOUT, and DOUTB at a first logic level (e.g., LOW) or a second logic level (e.g., HIGH). Example operations of the circuit 100 may be summarized in the following TABLE 1:

      TABLE 1
      GRESETB     PRESETB     RESETB       GINTSCNEN        DIN        DOUT
       HIGH         LOW        HIGH            X           HIGH        HIGH
       HIGH        HIGH         LOW            X            LOW         LOW
       HIGH         LOW         LOW            X            LOW         LOW
       HIGH        HIGH        HIGH           LOW          XORIN       XORIN
       HIGH        HIGH        HIGH          HIGH         SCANIN      SCANIN

The circuit 122 may comprise a transistor M1, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, a transistor M7, a gate 150, a gate 152, a gate 154, a gate 156, a gate 158, a gate 160, a gate 162. The transistors M1, M3, and M7 may be implemented as one or more NMOS transistors. The transistors M2, M4, M5, and M6 may be implemented as one or more PMOS transistors. However, other types and polarity transistors may be implemented accordingly to meet the design criteria of a particular application. The pair of transistors M1 and M2 and the pair of transistors M3 and M4 may be configured as CMOS switches. The gates 150, 158, 160, and 162 may be implemented, in one example, as inverters. The gates 152, 154, and 156 may be implemented, in one example, as NAND gates. However, other types of gates may be implemented to meet the design criteria of a particular application.

The signal GINTSCNEN may be presented to an input of the gate 150 and a first input of the gate 152. An output of the gate 150 may present a signal (e.g., GINTSCNENB) to a first input of the gate 154. The signals RESETB, PRESETB, and GRESETB may be presented to a first, a second, and a third input of the gate 156. An output of the gate 156 may present a signal to an input of the gate 158. An output of the gate 158 may present a signal to a second input of the gates 152 and 154. An output of the gate 152 may present a signal to an input of the gate 160 and a gate of the transistor M4. An output of the gate 160 may present a signal to a gate of the transistor M3. An output of the gate 154 may present a signal to an input of the gate 162 and a gate of the transistor M2. An output of the gate 162 may present a signal to a gate of the transistor M1.

The signal MRESET may be presented to a gate of the transistors M5 and M7. The signal PRESETB may be presented to a gate of the transistor M6. A source of the transistor M5 may be connected to a supply voltage (e.g., VCC). A drain of the transistor M5 may be connected to a source of the transistor M6. A source of the transistor M7 may be connected to a ground voltage (e.g., VSS). The signal XORIN may be presented to a first source/drain of the transistors M1 and M2. The signal SCANIN may be presented to a first source/drain of the transistors M3 and M4. A second source/drain of the transistors M1, M2, M3, and M4, and a drain of the transistors M6 and M7 may be connected to the output 146. The signal DIN may be presented at the output 146.

The circuit 124 may comprise a transistor M8, a transistor M9, a transistor M10, a transistor M11, a transistor M12, a transistor M13, a transistor M14, a transistor M15, a gate 164, a gate 166, a gate 168, a gate 170, a gate 172, a gate 174, and a gate 176. The transistors M9, M11, M13, and M15 may be implemented as one or more NMOS transistors. The transistors M8, M10, M12, and M14 may be implemented as one or more PMOS transistors. However, other types and polarity transistors may be implemented accordingly to meet the design criteria of a particular application. The pairs of transistors M8-M9, M10-M11, M12-M13, and M14-M15 may be configured as CMOS switches. The gates 164, 174, and 176 may be implemented, in one example, as inverters. The gates 166, 168, 170, and 172 may be implemented, in one example, as NAND gates. However, other types of gates may be implemented to meet the design criteria of a particular application.

The signal CLK may be presented to an input of the gate 164 and a gate of the transistors M8, M11, M13, and M14. The gate 164 may have an output that may present a signal (e.g., CLKB) to a gate of the transistors M9, M10, M12, and M15. The signal DIN may be presented to a first source/drain of the transistors M8 and M9. A second source/drain of the transistors M8 and M9 may be connected to (i) an input of the gate 168 and (ii) a first source/drain of the transistors M10 and M11. An output of the gate 168 may present a signal to a first input of the gate 166 and a first source/drain of the transistors M12 and M13. A second source/drain of the transistors M12 and M13 may present a signal to (i) a first source/drain of the transistors M14 and M15, (ii) a first input of the gate 172, and (iii) an input of the gate 174.

The signal PRESETB may be presented to a second input of the gates 166 and 172. An output of the gate 166 may present a signal to a second source/drain of the transistors M10 and M11. An output of the gate 172 may present a signal to a first input of the gate 170. The signal MRESETB may be presented to a second input of the gates 168 and 170. An output of the gate 170 may present a signal to a second source/drain of the transistors M14 and M15. The gate 174 may have an output that may present the signal DOUT to the output 116 of the circuit 124 and an input of the gate 176. The gate 176 may have an output that may present the signal DOUTB.

In one example, the interconnection of the transistors M8-M11, the gate 166, and the gate 168 may comprise a master flip flop. The interconnection of the transistors M12, M13, M14, M15, the gate 170, and the gate 172 may comprise a slave flip flop.

The circuit 100 may be asynchronously reset or preset in response to the signals RESETB, GRESETB, and PRESETB. In one example, the reset operation may have priority. When the circuit 100 is reset or preset, the signals XORIN and SCANIN are generally deselected. When the signals XORIN and SCANIN are deselected, the signal DIN may be prevented from floating by the transistors M5-M7. In one example, the transistors M5-M7 may be configured to pull the signal DIN (and the input 148) HIGH in response to the signal PRESETB or LOW in response to one or more of the signals RESETB and GRESETB. However, other signal polarities may be implemented to meet the design criteria of a particular application. In one example, signal levels of the circuit 100 during asynchronous reset and preset operations may be summarized in the following TABLE 2:

       TABLE 2
      CONDITION     GRESETB    PRESETB   RESETB     GINTSCNEN     DIN    DOUT
       PRESET        HIGH        LOW      HIGH          X        HIGH    HIGH
        RESET        HIGH       HIGH       LOW          X         LOW     LOW
        RESET        HIGH        LOW       LOW          X         LOW     LOW
        RESET         LOW         X         X           X         LOW     LOW

       TABLE 3
      CONDITION     DIN    DOUT     CLK   SIGNAL PATH
        RESET       LOW     LOW     LOW   gate 170, to transistors M14
                                          and M15, to gate 174
        RESET       LOW     LOW    HIGH   gate 168, to transistors M12
                                          and M13 to gate 174
       PRESET      HIGH    HIGH     LOW   gate 172, to gate 170, to
                                          transistors M14 and M15,
                                          to gate 174
       PRESET      HIGH    HIGH    HIGH   gate 166, to transistors M10
                                          and M11, to gate 168, to
                                          transistors M12 and M13,
                                          to gate 174