BACKGROUND AND SUMMARY OF THE INVENTION

The effect of contact bounce of switches on the output of an electronic circuit has been a problem for a considerable time. Many types of electronic circuits have been invented for eliminating chatter in the output of an electronic circuit due to the contact bounce of input switches. Several circuits are disclosed in U.S. Pat. No. to Yukuo Kodama, U.S. Pat. No. 3,989,960, issued Nov. 2, 1976; to Izuhiko Nishimura, U.S. Pat. No. 4,057,738, issued Nov. 8, 1977; to Milton E. Hilliard, Jr., and Daniel J. Provine, U.S. Pat. No. 4,159,497, issued June 26, 1979; and to Borys Zuk, U.S. Pat. No. 4,185,210, issued Jan. 22, 1980.

The present invention is concerned with electronic circuit having a pair of switch means whose outputs are compared periodically upon the command of a clock signal so that upon a switch connected to the input of one of the switch means must reach a steady state operation with no contact bounce before the output of the comparison to coincide with the input signal is provided. Specifically, the invention is applicable with at least a pair of input signals to provide a binary code upon the operation of the switches in the input circuit. The output is provided after the contact bounce has terminated. The invention is even more applicable to a three input circuit which can generate eight functions of binary code where greater error can result for providing no change in the output until the input switches have returned to a stable state.

BRIEF DESCRIPTION OF THE DRAWINGS

The single FIGURE is a circuit diagram of the electronic circuit having a three input binary coded input circuit for providing a three circuit binary coded output.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to the single FIGURE, an electronic circuit 10 eliminates the effect of contact bounce of an input signal from an input switch means 11 on an output circuit 12. Input circuit 11 might be slide switches or membrane keyboards used to generate a binary code over input circuits 13, 14 and 15 connected to conventional voltage generating circuits 20, and to the input of electronic circuit 10 by conductors 22, 23 and 24. Circuits 20 drop the input voltage when any one of the input switches of circuit 11 are open. Circuit 20 has a plurality of diodes at 21 for gate oxide protection as described in the RCA Application Note ICN6218 of the RCA Solid Stage Data Book SSD203A, 1973 Edition.

Circuit 10 has a first group 25 of switch means 30, 30' and 30" of the D-flip-flop gate type, specifically Motorola Type No. MC14013B. Each of the switch means of the first group has two input circuits 31 and 32, an output circuit 33, and a reset circuit 34 which are labeled using the same prime and double prime code. Specifically, input circuit 32 is made up of two circuits connected to a timing circuit or source of clock timing pulses 35 which has two outputs 40 and 41 for providing the 64 Hz and 64 Hz signals or the clock timing pulse signals at different voltages, such as 5 volts and 0.

A second group 36 of switch means 42, 42' and 42" also have two input circuits 43 and 44 and output circuit 45, and a reset circuit 50.

The inputs 31, 31' and 31" of the first group of switch means are connected to the input conductors 22, 23 and 24, and the outputs 33, 33' and 33" are connected to the inputs 43, 43' and 43" of the second group of switch means 42 as well as to the input 50 of another group of switch means 51. Switch means 51 might be conventional exclusive NOR gates of the type manufactured by Motorola, Inc., Part No. MC14077B, which have two inputs 50 and 52, and an output 53. The input 52 is connected to the output of the gate 42.

Another switch means or gate 54, having a plurality of inputs 55 and 60 is similar to a Motorola NAND gate MC14012B which, upon all the input signals being positive, a negative output exists on the output 59. Inputs 55 are connected to the outputs of the switch means 51 and input 60 is connected to the timing circuit 41.

Another group 56 of switch means 61, similar to switch means 30 and 42, have input circuits 62 and 63, an output circuit 64 and a reset circuit 65. Each of the finput circuits 62 of gate 61 are connected to the output 45 of gate 42 and the input 63 is connected to the output of switch means 54 to provide the 64 and 64 Hz timing pulse signals over conductors 70 and 71 by an inverter 72 of the type manufactured by Motorola, Inc., Part No. MC14049B. The output 64 of each of the switch means 61 is connected over conductors 73, 74 and 75 to provide the binary encoded input to the output circuit 12.

A reset signal is available from the reset signal circuit 80 over a conductor 81 which is connected to each of the reset inputs of the gates 30, 42 and 61 to selectively reset the flip-flop circuits after the circuit is initially powered up to place the circuit 10 back in the normal condition.

Operation of the Preferred Embodiment

The binary coded signal over conductors 13, 14 and 15 from the input circuit 11 might be provided by any type of switch means which has contact bounce. To eliminate the contact bounce, circuit 10 prevents the binary coded signal from entering the input of the output circuit 12 over conductors 73, 74 and 75, until the contacts of the switch means have stabilized so a true binary coded signal as produced in the input circuit 11 is transmitted to the output circuit 12. Assuming that there is no signal over conductors 22, 23 and 24, and the gates of groups 25, 36 and 56 are reset to have no output, a binary encoded input of 111 is generated from input circuit 11. Normally, due to contact bounce, without circuit 10, output circuit 12 would receive one or more of the following codes: 001, 010, 011, 100, 101, and 110. With the circuit 10, a debounce time range from 1.5/clock frequency to 2.5/clock frequency and thus with a 64 Hz clock frequency the times are 24 milliseconds to 40 milliseconds.

Let us assume that, due to the contact bounce, gates 30, 30' and 30" receive an input at the input circuit 31 of 100 at the time the timing pulse was received by circuit 32. The output of the group of gates 30 would be 100. At the next timing pulse, if the bounce had terminated, the input to gates 30, 30' and 30" would be 111; however, while the exclusive NOR gate 51 would provide an output, the exclusive NOR gate 51' and 51" would receive different outputs as gates 30' and 42' upon receiving the next clock pulse would provide a 1 and a 0 output to the input of gate 51'. At the next timing pulse, the exclusive NOR gate 51 would all be operative and the NAND gate 54 would allow a timing pulse to the gate 61 to provide the output to the output circuit 12 similar to the 111 binary input at 21.