BACKGROUND AND SUMMARY OF THE INVENTION

The present invention relates to integrated circuit structures and fabrication methods, especially to the fabrication of DRAM Arrays.

Background: Capacitor-Under-Bitline DRAM

DRAM cells have a capacitor buried under, or stacked over, the transistor associated with it. Where the capacitor is stacked over the transistor, there are two types of cells: the Capacitor Over Bitline (COB) cell and the Capacitor Under Bitline (CUB). FIG. 4 shows an example of a CUB DRAM architecture, with capacitor structures 30, composed of the conductive storage node layer 16, dielectric layer 18, and plate layer 20, rising above the gates 10 of the transistors in the DRAM array. The use of polysilicon to form the conductive plate layer is changing to the use of metals, such as TiN, to avoid depletion layer formation in the capacitor, which in turns lowers cell capacitance. Bitline 22 runs above the capacitors, with the bitline contact 24 descending through the top capacitor electrode (plate) 20 to contact underlying devices or risers, such as the bitline contact plug 12. As the bitline contact is etched through the conductive plate layer of the capacitor, shorting to this plate by the via must be avoided at all costs, or the DRAM will lose functionality due to inadvertent capacitor leak-age/discharge. Current state-of-art technology utilizes the following flow:

a.) Etch via through the capacitor plate;

b.) Ash and post-etch clean (in no particular order);

c.) Wet etch to isotropically remove that portion of the plate which is immediately adjacent to the via, with e.g. H2O2- or HF-containing aqueous solutions;

d.) conformal deposition and etchback of dielectric 26, generally SiN or SiO2, which insulates the via/plate junction (or partial oxidation of the plate layer if it is still polysilicon).

Simplifying Plate/Via Isolation in CUB DRAM

The present application discloses using a dry (plasma) process to accomplish both the post-etch clean and wet etch steps. Previous work has shown that the use of dilute CFx, in O2-rich remote plasmas will isotropically etch TiN from the top of A1 metallizations. Using this process to remove post-etch residue from the via replaces expensive and environmentally-unfriendly solvent cleans, while simultaneously retracting the capacitor plate material from the via sidewalls.

Advantages of the disclosed methods and structures include simplification of the fabrication process, which in turn reduces costs.

BRIEF DESCRIPTION OF THE DRAWINGS

The disclosed inventions will be described with reference to the accompanying drawings, which show important sample embodiments of the invention and which are incorporated in the specification hereof by reference, wherein:

FIGS. 1A-C are flow charts showing key steps in various embodiments of the disclosed process for retracting the plate layer from around a contact.

FIGS. 2A-C shows a cross-section of a partially fabricated integrated circuit structure at various points during one embodiment of the disclosed process.

FIGS. 3A-B shows a cross-section of a partially fabricated integrated circuit structure at various points during an alternate embodiment of the disclosed process.

FIG. 4 shows a cross-section of one type of CUB DRAM array which can be fabricated using the disclosed process.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The numerous innovative teachings of the present application will be described with particular reference to the presently preferred embodiment. However, it should be understood that this class of embodiments provides only a few examples of the many advantageous uses of the innovative teachings herein. In general, statements made in the specification of the present application do not necessarily delimit any of the various claimed inventions. Moreover, some statements may apply to some inventive features but not to others.

First Embodiment: One Step Contact Etch

FIG. 1A shows a first embodiment of the process, and will now be discussed. Prior to the disclosed process for isolating the via from the plate layer, the DRAM array will be formed. Only a general discussion of this process will be given here, as there are many methods by which this array can be formed.

Isolation structures, such as the STI isolation of FIG. 3 are formed, followed by the formation of the DRAM transistors. A dielectric layer is deposited and bitline and storage node contacts are formed. Capacitors 30 are formed, having plate layer 20, which is an extension of one node of the capacitors (step 101). In this embodiment, the plate layer consists of approximately 100 nm of TiN. The capacitors are surrounded by dielectric layer 32 and overlain by a further dielectric layer 34, both generally an oxide.

FIG. 2A shows a simplified view of the bitline contact as it descends through the plate layer. Resist PR has been deposited and patterned (step 102). This is followed by the etch (step 103) of the contact 35, which passes through the unpatterned conductive plate layer 25. Immediately after the contact etch, the resist is ashed. A further dry etch (step 104), to etch back or retract the TiN plate layer, is performed with the following parameters:

              Source gas (O.sub.2)             4,000 sccm
              Source gas (C.sub.2 F.sub.6)                 6 sccm
              Pressure                        1.5 Torr
              RF power                        850 W