CROSS-REFERENCE TO RELATED APPLICATIONS

Not applicable.

BRIEF DESCRIPTION OF THE DRAWINGS

For a detailed description of the preferred embodiments of the invention, reference will now be made to the accompanying drawings in which:

FIG. 1 shows a computer system embodying the preferred embodiment of the invention in which multiple fan controllers are present and interconnected so as to provide a hardware-based fault response.

NOTATION AND NOMENCLATURE

Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, computer companies may refer to a component and sub-components by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms "including" and "comprising" are used in an open-ended fashion, and thus should be interpreted to mean "including, but not limited to . . . ". Also, the term "couple" or "couples" is intended to mean either a direct or indirect electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. In addition, no distinction is made between a "processor," "microprocessor," "microcontroller," or "central processing unit" ("CPU") for purposes of this disclosure. To the extent that any term is not specially defined in this specification, the intent is that the term is to be given its plain and ordinary meaning.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now to FIG. 1, system 100 is shown constructed in accordance with a preferred embodiment of the invention. As shown, system 100 includes one or more host processors 102, a north bridge 110, main memory 120, a south bridge 130, and one or more fan controllers 140a and 140b each coupled to one or more fans 150. The north bridge couples to the processors 102, memory 120 and the south bridge 130. The bus 125, which may be a peripheral component interconnect bus, interconnecting the north and south bridges 110, 130 may have one or more devices such as modems, network interface cards ("NICs"), and the like attached thereto. Other architectures besides that shown in FIG. 1 are possible also; the architecture in FIG. 1 is merely exemplary of one suitable embodiment.

The system shown in FIG. 1 includes two fan controllers 140a, 140b, but more than two controllers can be included or only a single controller if desired. The fan controllers are shown coupled to the south bridge 130, but alternatively can be coupled to other logic within the system 100, such as the north bridge 110 or host processor 102 or a baseboard controller (not shown). Further, each controller 140 is shown coupled to two fans 150, but additional fans can be coupled to each controller if desired or only a single fan. Each fan 150 receives power from the system's power supply (not shown) and control signals from the fan controllers 140. The control signals are generally provided via bus 136 from the south bridge 130 to the controllers 140. Bus 136 can be any suitable type of bus such as an I²C bus. The fan controllers 140 are capable of causing their fan(s) to operate at more than one speed which is programmable by the host processor 102.

In accordance with the preferred embodiment of the invention, the fan controllers 140a and 140b are connected together so as to provide a hardware-based fault response. That is, on a broad level, an error condition experienced by one fan controller or its fan(s) is transmitted to the other fan controller without the involvement of external controlling logic such as the host processor. This feature can be implemented in a variety of ways. For example, in FIG. 1, each fan controller connects to a FAULT signal 144 which is used to communicate faults between controllers. The FAULT signal preferably is a bi-directional signal meaning that each fan controller 140a, 140b can assert the signal or receive it from another fan controller which asserted it. When a controller 140 detects a fault with one of its own fans, that controller asserts the FAULT signal. The other fan controller in the system detects the assertion of the FAULT signal and responds in a predetermined or programmed manner. For example, a controller receiving a FAULT signal asserted by another controller may respond by causing one or all of its fans to spin in a high speed mode. This permits the failure of a fan or fans connected to one fan controller to be detected by another fan controller which can respond by running its fan(s) at a faster speed to make up for the loss of airflow caused by the failed fans. This process advantageously does not require processor involvement. The FAULT signal also can be provided to the south bridge 130 or an interrupt routing device (not shown) so that the host processor 102 can also be alerted of the existence of a fault.

Preferably, the FAULT signal remains asserted even after the error condition subsides. The FAULT signal remains asserted until cleared by software executing on the host processor 102. The FAULT signal 136 may also be provided to the south bridge 130 as shown so that the host processor can be made aware of the existence of a fault condition. Also, each fan controller includes an interrupt output signal which preferably are wire-OR'd and provided to the south bridge 130 as shown. Alternatively, the interrupts can be individually connected to the south bridge 130 or other logic. The interrupt signal can be asserted by a controller upon any one or more of various predetermined or programmed conditions such as a fan that is hot plugged (insertion or removal) or a fault.

The fan controllers 140 preferably have one or more registers 142a and 142b that are used for programming and status purposes. The registers 142a, 142b include a plurality of bits some of which provide status information, and others of which can be used to control various aspects of the fan controller. Those bits that are useful for providing the inter-controller fault detection and control include: